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ISO 15118-2 Plug-and-Charge: Hardware Implementation Requirements

May 2025  ·  10 min read

What ISO 15118-2 Plug-and-Charge means for hardware designers — Power Line Communication IC selection, PCB layout constraints, PLC coupling network design, and HomePlug GreenPHY timing.

ISO 15118-2 Plug-and-Charge: Hardware Implementation Requirements

ISO 15118-2 Plug-and-Charge (PnC) is the standard that enables an EV to authenticate itself to a charger and initiate a charging session without any user interaction — the cable is the credential. Implementing PnC correctly at the hardware level requires specific choices around the Power Line Communication (PLC) subsystem that are not obvious from reading the standard alone.

The Physical Layer: HomePlug GreenPHY

ISO 15118-2 uses HomePlug GreenPHY (HPGP) as the physical layer for the vehicle-to-charger (V2G) communication. HPGP operates on the Control Pilot (CP) signal line — the same pilot that handles basic IEC 61851-1 proximity and state signalling.

HPGP modulates a narrowband OFDM signal (1.8–30MHz) onto the CP line alongside the 1kHz PWM state signal. This means the CP line simultaneously carries:

  1. The 1kHz square wave for IEC 61851 state machine signalling
  2. The HPGP OFDM data signal for ISO 15118-2 higher-layer communication

Hardware designers must ensure the PLC coupling network passes the HPGP band (1.8–30MHz) while not disrupting the 1kHz PWM signal, and vice versa.

PLC IC Selection

The dominant ICs for HPGP implementation in EVSE are from Qualcomm Atheros (QCA7000/7005) and Lumissil (IS-PLC100). Both are single-chip HPGP MAC+PHY solutions designed for automotive and EVSE applications.

Key selection criteria:

  • SPI or UART interface: Most embedded controllers integrate via SPI. Confirm the SPI clock speed supported by your application processor.
  • Temperature range: The PLC IC must operate across the EVSE temperature range (typically −40°C to +85°C for outdoor installations)
  • Package: QCA7000 is available in a 48-pin QFN, suitable for dense PCB layouts

Coupling Network Design

The coupling network connects the PLC IC to the CP line without disturbing the 1kHz pilot circuit. A typical coupling network consists of:

  1. High-pass filter (coupling capacitor + series inductor) passing the HPGP band (>1.8MHz) from the PLC IC to the CP line
  2. Low-pass filter on the CP line side isolating the 1kHz pilot circuitry from the RF signal

Component values must be verified by simulation — the coupling network interacts with the impedance of the CP cable (up to 15m in IEC 61851), the vehicle's CP input impedance, and the HPGP transmit power level.

PCB layout considerations:

  • Keep the coupling network components within 20mm of the PLC IC
  • Use a solid ground plane beneath the coupling network — avoid splits under the RF path
  • The CP connection to the coupling network should be a short, direct trace — do not route it near switching power stages

Timing Constraints

ISO 15118-2 specifies timing requirements for the transition from IEC 61851 basic signalling to HPGP communication. The EVSE must detect that the vehicle supports HPGP (by monitoring for HPGP traffic on the CP line after State B) within a defined timeout.

This timing constraint means the HPGP IC must be initialised and ready to receive traffic quickly after the cable is connected. The firmware must not delay HPGP initialisation behind other power-on tasks. In practice, keep the HPGP IC on a separate power domain that is energised as soon as the CP line is activated, independent of the main converter startup sequence.

Certificate Storage

PnC requires the EVSE to store a provisioning certificate (from the CPO certificate chain) and to perform TLS certificate verification during each session. This requires:

  • Non-volatile storage for certificates (at minimum, the CPO leaf certificate and intermediate CA certificates)
  • A processor with TLS stack capability (or hardware TLS offload)

If your EVSE controller is a resource-constrained embedded device, add a dedicated crypto IC (ATECC608A or similar) for certificate storage and ECC operations. The TLS handshake for ISO 15118-2 must complete within the protocol timeout — characterise the handshake time on your target hardware before committing to the platform.

Conclusion

ISO 15118-2 PnC hardware implementation is primarily a PLC coupling network design problem combined with a firmware architecture problem. The physical layer IC selection is straightforward; the coupling network design and the timing/TLS constraints require careful attention to avoid costly re-spins late in the project.

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